A Novel Approach for Designing a D-flip Flop Using Mtcmos Technique for Reducing Power Consumption

Power consumption is a major bottleneck of system performance. A large portion of the on chip power is consumed by the clock system. It is made of the any integrated circuit, clock distribution network and flop-flops. A new system will considerably reduce the number of transistor it will lead to the reduction in clocking power and also improve the overall power consumption. Various design techniques used for a low power clocking system. Among those techniques Clocked Pair Shared Flip Flop(CPSFF) consume least power than Conditional Data Mapping FlipFlop(CDMFF), Conditional Discharge Flip Flop(CDFF) and Conventional double Edge Triggered Flip-Flop (DEFF). A proposed novel Clocked Pair Shared FlipFlop(CPSFF) using Multi-Threshold voltage CMOS(MTCMOS) technique which reduces the power consumption approximately by 20% to 90% than the original CPSFF. Simulation using Tanner Tool version 13.00 with 250 nanometer technology. The power consumption is calculated by T Spice. The proposed work clock pair shared flip flop using MTCMOS technique is more efficient than all other designs. Key wordsMTCMOS technique, integrated circuit, CPSFF, CDMFF ,CDFF, DEFF, power delay.